1. Field of the Invention
The present invention relates to a bit rate converter for converting the fixed bit rate of an input signal to a different bit rate.
2. Description of the Related Art
Bit rate converters have been widely used in transmission systems and digital data processing systems. Consider the case where an input signal of a fixed bit rate is converted to a higher bit rate signal structured in frames and having an overhead (OH) and a redundancy code included therein. The input signal is written on a buffer memory according to a write clock of the fixed bit rate. The written signal is read out in frames from the buffer memory according to a read clock of the higher bit rate while adding an overhead (OH) and a redundancy code thereto. At a receiver end, the overhead and redundancy code are terminated and the high bit rate of the received data is converted to the original fixed bit rate.
In addition, there have been known pulse stuffing techniques to insert one or more stuff pulses in the frames based on a phase difference between a write timing and a read timing achieve bit rate adjustment. For example, see U.S. Pat. Nos. 4,920,547 and 5,276,688.
In general, the phase difference is monitored by a phase comparator comparing the write address and the read address on the buffer memory. The phase difference varies in a period of the frame. More specifically, when the written data are read out from the buffer memory according to the read clock of the higher bit rate, the phase difference becomes smaller because the frequency of the read clock is higher than that of the write clock. When the read clock stops to insert the overhead and redundancy code, the phase difference increases sharply because the data writing is continuously performed according to the write clock. Accordingly, the phase difference varies in such a manner from frame to frame (see FIG. 5B).
FIG. 5B shows a time-varying phase difference in the case of n-bit butter memory used for bit rate adjustment. As shown in FIG. 5B, when the input signal is normally received, a phase difference varies in a period of one frame within a predetermined proper range having a center phase difference of n/2. In such a case, the bit rate adjustment is normally performed without any error or data slipping.
In the event that the write clock of the fixed bit rate stops due to some failure, the phase difference reduces sharply because the readout operation is continuously performed according to the read clock of the higher bit rate. Finally, the phase difference becomes zero, resulting in underflow status (see FIG. 6B).
Contrarily, there are cases where the phase difference reaches the depth (n-bit) of the buffer memory due to jitter or wander of the write clock, resulting in overflow status.
According to the conventional circuit, however, in a case of such an overflow or underflow status, the phase difference is forced to be reset to the initial value of n/2. Such a reset operation causes the data written in the buffer memory to be cleared. Therefore, some data slips away from the buffer memory, leading to error status.